★ Classic rhythm scaffolding
Master clock (16ths) → Clock In · POW2 mode · Out 1 = 8ths · Out 2 = quarters · Out 3 = half · use for kick/snare/hat
Clock/trigger divider with 7 outputs and three switchable divisor sets: powers of two, primes, or integers. Two output modes — Gate (50% binary) and Trigger (AND'd with clock, inherits its pulsewidth). Jumper-selectable clock edge, reset polarity, output polarity.
Patch Ideas · 6
★ Prime polyrhythm drone
PRIME mode · Out 4 (÷7), Out 5 (÷11), Out 6 (÷13) each trigger slow envelopes on separate drones
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★ Seven-step odd meter
INT mode · Out 6 (÷7) resets a sequencer every seven clocks for 7/8 phrasing
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Reset-locked fills
Bar-length reset keeps divider phase aligned after tempo changes or on-the-fly re-patching
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Trigger-mode hi-hat shuffle
Trigger mode inherits clock pulsewidth — shape clock with narrow gates to get tight hi-hat triggers on divided outputs
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Slow LFO from divided clock
POW2 mode · Out 7 (÷128) drives a slew limiter to produce a smooth minute-long pseudo-LFO synced to clock
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Behaviors
Binary bar/beat divisions POW2 mode
Standard powers-of-two divisions produce musical bar, half, quarter, eighth relationships when clock is a 16th or 32nd. Ideal for song-structure gates.
Prime-number polyrhythms PRIME mode
Divisors share no common factors, so outputs drift apart maximally. ÷11 and ÷13 only re-align every 143 clocks, yielding long, non-repeating rhythmic textures.
Odd-meter integer grid INT mode
Sequential integer divides give triplet, quintuplet, septuplet relationships useful for odd-meter patterns that still resolve periodically.
Trigger mode pulsewidth masking Output Mode: Trigger
Outputs are AND'd with the raw clock, so each divided pulse takes the clock's pulsewidth rather than a 50% gate. Useful for drum-style triggers that sit inside the clock phase instead of stretching across it.
Synchronous reset on bar boundary bar-length pulse → Reset In
A reset pulse per bar realigns every output to phase 0, preventing drift when the divider is re-entered mid-song or when the clock is stopped/started.
Hardware-configured polarity internal jumpers
Clock edge, output polarity, reset level vs edge, and reset polarity are all jumper-selectable on the PCB — no front-panel way to change. Relevant when interfacing non-Doepfer gate standards.
Controls
| Divisor set | Division Mode | 3-position switch picks which divisor set the seven outputs use. POW2: 2·4·8·16·32·64·128 · PRIME: 2·3·5·7·11·13·17 · INT: 2·3·4·5·6·7·8 |
| Pulse shape | Output Mode | Selects between standard divided gates and trigger-masked pulses. Gate: 50% duty binary divide · Trigger: output AND clock, pulsewidth = clock pulsewidth |
| Internal | Clock Edge (jumper) | Internal jumper selects rising or falling edge of clock input as the count trigger. installed: rising · removed: falling |
| Internal | Gate Output Polarity (jumper) | Inverts all seven outputs when removed. installed: normal · removed: inverted |
| Internal | Reset Behaviour (jumper) | Chooses level-triggered vs edge-triggered reset. installed: level · removed: edge |
| Internal | Reset Input Polarity (jumper) | Polarity for reset: level mode picks high/low; edge mode picks rising/falling. installed: high/rising · removed: low/falling |
I/O
IN · 2
- Clock In digital / gate GATEDigital clock/trigger input. Accepts any pulse source — LFO square, MIDI-sync gate, sequencer trigger.
- Reset In digital / gate GATESynchronously resets all divider counters. Level or edge mode and polarity are jumper-selected.
OUT · 7
- Out 1 (÷2) 0 to ~+10V CLKDivided clock — ÷2 in all three modes.
- Out 2 0 to ~+10VPOW2: ÷4 · PRIME: ÷3 · INT: ÷3.
- Out 3 0 to ~+10VPOW2: ÷8 · PRIME: ÷5 · INT: ÷4.
- Out 4 0 to ~+10VPOW2: ÷16 · PRIME: ÷7 · INT: ÷5.
- Out 5 0 to ~+10VPOW2: ÷32 · PRIME: ÷11 · INT: ÷6.
- Out 6 0 to ~+10VPOW2: ÷64 · PRIME: ÷13 · INT: ÷7.
- Out 7 0 to ~+10VPOW2: ÷128 · PRIME: ÷17 · INT: ÷8.